1. Field of the Invention
The present invention relates to a BGA package and a method of manufacturing the same. Particularly, the present invention relates to a BGA package which has superior reliability, showing excellent interfacial properties and resistance to external impact. Also, the present invention is concerned with a method of manufacturing the BGA package, in which a bend having a planar upper surface and a slanted periphery is formed between a solder contact side of a bonding pad and an insulation layer, thereby providing an increased bonding area for a solder ball.
2. Description of the Related Art
Although integrated circuits have been developed for slimness and lightness, the number of leads extending from integrated circuit packages is increasing rather than decreasing. As a solution to the problem resulting from a small package carrier requiring a large number of leads, a PGA (pin grid array) carrier has been developed. Able as it is to be provided with many leads to its small area, the PGA carrier suffers from disadvantages that pins or leads are so weak that they break readily and that there are limits to high density integration.
An approach to overcoming the disadvantages of PGA is to use recently popularized BGA package substrates. BGA package substrates employ solder balls, which are finer than pins, thereby allowing high density integration thereon. Mostly, BGA package substrates are used for mounting semiconductor chips.
In order to better understand the background of the present invention, a description is given of a conventional BGA package substrate, below.
With reference to FIG. 1, a conventional semiconductor chip-mounted BGA package provided with solder balls 60 instead of pins is depicted in a cross sectional view.
First, a plurality of CCLs (copper clad laminates) 10 is prepared, each CCL 10 undergoing a typical photolithographic process to form a predetermined circuit pattern thereon.
Next, the CCLs 10, each having a predetermined circuit pattern thereon, are pressed against each other to provide a laminate structure which is then processed to form a via hole 20, followed by plating the via hole 20 with a copper foil 30 to electrically interconnect the circuit patterns formed on each CCL 10.
On the copper foil 30 formed on a side of the laminated CCL structure, a circuit pattern for a semiconductor chip 40-mounting bonding pad, e.g. a bond finger 50, is constructed by a photolithographic process. Likewise, a circuit pattern for bonding pads to which solder balls 60 are attached, that is, a circuit pattern for solder pads 70, is also constructed on a copper foil 30 formed on another side of the CCL structure.
Following the formation of the circuit patterns for the bonding pads 50 and 70 on the copper foils 30 of the CCL 10, PSR (photo imageable solder resist mask) ink is applied to form an insulation layer 80 with the aim of protecting the circuit patterns on the copper foils 30 as well as preventing the formation of a solder bridge between the circuit patterns during a soldering process.
Subsequently, with the aid of a diazo film having thereon a circuit pattern for exposing the bonding pad, a circuit process is conducted to remove the insulation layer 80 coated on the area where the bond finger 50 or the solder pad 70 will be formed.
After the formation of the bonding pad, such as the bond finger 50 or the solder pad 70, a finishing process for preventing the oxidation of the bonding pad is conducted to form a Ni/Au-plated layer on the bonding pad by electroless gold plating.
In more detail, the bonding pad, e.g., the bonding finger 50 or the solder pad 70, is plated with nickel to form a nickel-plated layer 91 to a predetermined height, e.g., 3-5 μm.
Gold, when applied to a bare bonding pad 50 or 70, diffuses into the copper texture of the bonding pad, so that the gold-plated layer cannot be subjected to the finishing process. Accordingly, nickel plating precedes gold plating in order to prevent gold, when plated, from diffusing into the copper texture.
Next, a gold-plated layer 92 is formed to a predetermined height, for example, 0.03-0.07 μm on the nickel-plated layer 91 so as to impart affinity for the solder balls 60. Therefore, a BGA package is obtained, with the bond finger for mounting a semiconductor device and the solder pad for attaching solder being finished.
In this conventional BGA package, the formation of the Ni/Au-plated layer 90 not only prevents the bonding pad, made from electrically conducting metal such as copper (Cu), that is, the solder pad 70, from being oxidized, but also provides the bonding pad with greater affinity for the solder balls 60; however, intermetallic compounds are produced due to the reaction between the nickel of the plated layer 90 and the tin of the solder balls 60.
A high-speed impact test such as a drop test revealed that cracking readily occurs at the interface between the Ni/Au-plated layer 90 and the solder balls due to the brittleness of Au in the presence of the intermetallic compounds including Au formed by the reaction of the Ni/Au layer with the solder, and thus that the solder balls 60 are readily detected from the solder pads.
As a solution to the problem, a BGA packaging process is suggested which employs an OSP (organic solderability preservative), instead of the Ni/Au-plated layer 90, in finishing the semiconductor chip-mounting bonding pad or the solder-bonding solder pad.
In lieu of the formation of the Ni/Au-plated layer 90 on the solder pad to which solder is attached, an OSP is layered on the solder pad to conduct the finishing process for the open solder pad.
Thereafter, the OSP-coated BGA package substrate is subjected to an in-line process consisting of prebake, die attach, die attach curing, plasma and wire bonding, through which a semiconductor device is connected onto the bonding pad formed on a side of the BGA package substrate.
The in-line process through which a semiconductor device is attached onto the bonding pad is followed by a back-end process consisting of prebake, plasma, pre-mold curing, post-mold curing, solder attach and IR reflower, through which a solder is attached to the solder pad formed on another side of the BGA package substrate.
However, the BGA package process using an OSP is disadvantageous in that the OSP applied to the plated layer where the solder pad is formed is damaged by heat during the in-line process or the back-end process as shown in FIG. 3. Especially, the PMC step of the back-end process, which is conducted at 175° C. or higher, causes fetal damage to the OSP.
With reference to FIG. 4, a ball shear test shows that the OSP thermally damaged during the in-line process or the back-end process remains in the plated layer at which the bonding finger or solder pad of the BGA package substrate is formed.
As shown in FIG. 5, when a solder is jointed to a planar, plated layer 170 which is not etched in a direction to a predetermined depth and in which a thermally damaged OSP 200 remains, the remaining OSP 200 decreases the bonding area between the plated layer 170 and the solder balls 60 and prevents the reaction between the copper of the plated layer 170 and the tin of the solder balls 60 to inhibit the formation of intermetallic compounds 700.
As a result, the BGA package becomes unreliable, showing the formation of a non-wetting zone on a solder side and poor interfacial properties. For example, as shown in FIG. 6, the solder balls 60 are not bonded to the plated layer 170 or readily detaches upon external impact.